The present invention relates to non-volatile memory systems, and more specifically, to a memory system having a test mode of operation in which the data contained in the memory cells can be verified using the internal data verification process which is part of a programming or erase operation. This provides a test engineer with more reliable status information regarding the data contained in the memory cells then that obtained by performing a read operation or using external verification methods.
In early integrated circuit memory systems, the detailed operation of the memory system was controlled directly by a processor unit which utilized the memory. This was referred to as external control of the memory system operations because the control means was external to the memory itself. Since the operation of many memory systems requires a substantial amount of processor overhead, and since different manufacturers require different operations for optimizing their particular memories, many such systems now include an internal state machine (ISM) for controlling the operation of the memory system. The internal state machine controls the execution of the primary operations of the memory system, including reading, programming and erasing of the memory cells. Each of these primary operations is comprised of a large number of sub-operations which are necessary to carry out the primary operations, with these sub-operations also being controlled by the state machine.
FIG. 1 is a functional block diagram of a conventional non-volatile memory system 1. The core of memory system 1 is an array 12 of memory cells. The individual cells in array 12 (not shown) are arranged in rows and columns, with there being, for example, a total of 256K eight bit words stored in array 12. The individual memory cells are accessed by using an eighteen bit address A0-A17, which is input by means of address pins 13. Nine of the eighteen address bits are used by X decoder 14 to select the row of array 12 in which a desired memory cell is located and the remaining nine bits are used by Y decoder 16 to select the column of array 12 in which the desired cell is located. Sense amplifiers 50 are used to read the data contained in a memory cell during a read operation or during a data verification step in which the state of a cell is determined after a programming, pre-programming, or erase operation. The sense amplifier circuitry can be combined with the data compare and verify circuits used to compare the state of a cell to a desired state or to the input data used in programming the cell.
Programming or erasing of the memory cells in array 12 is carried out by applying the appropriate voltages to the source, drain, and control gate of a cell for an appropriate time period. This causes electrons to tunnel or be injected from a channel region to a floating gate. The amount of charge residing on the floating gate determines the voltage required on the control gate in order to cause the device to conduct current between the source and drain regions. This is termed the threshold voltage, Vth, of the cell. Conduction represents an xe2x80x9conxe2x80x9d or erased state of the device and corresponds to a logic value of one. An xe2x80x9coffxe2x80x9d or programmed state is one in which current is not conducted between the source and drain regions and corresponds to a logic value of zero. By setting the threshold voltage of the cell to an appropriate value, the cell can be made to either conduct or not conduct current for a given set of applied voltages. Thus, by determining whether a cell conducts current at a given set of applied voltages, the sate of the cell (programmed or erased) can be found.
Memory system 1 contains internal state machine (ISM) 20 which controls the data processing operations and sub-operations performed on memory array 12. These include the steps necessary for carrying out programming, reading and erasing operations on the memory cells of array 12. In addition, internal state machine 20 controls such operations as reading or clearing status register 26, identifying memory system 1 in response to an identification command, and suspending an erase operation. State machine 20 functions to reduce the overhead required of an external processor (not depicted) typically used in association with memory system 1.
For example, if memory cell array 12 is to be erased (typically, all or large blocks of cells are erased at the same time), the external processor causes the output enable pin {overscore (OE)} to be inactive (high), and the chip enable {overscore (CE)} and write enable {overscore (WE)} pins to be active (low). The processor then issues an 8 bit command 20H (0010 0000) on data I/O pins 15 (DQ0-DQ7), typically called an Erase Setup command. This is followed by the issuance of a second eight bit command DOH (1101 0000), typically called an Erase Confirm command. Two separate commands are used to initiate the erase operation in order to minimize the possibility of inadvertently beginning an erase procedure.
The commands issued on I/O pins 15 are transferred to data input buffer 22 and then to command execution logic unit 24. Command execution logic unit 24 receives and interprets the commands used to instruct state machine 20 to initiate and control the steps required for erasing array 12 or carrying out another desired operation. If a programming operation is being executed, the data to be programmed into the memory cells is input using I/O pins 15, transferred to input buffer 22, and then placed in input data latch 30. The data in latch 30 is then made available to sense amplifier circuitry 50 for the programming and data verification operations. Once a desired operation sequence is completed, state machine 20 updates 8 bit status register 26. The contents of status register 26 is transferred to data output buffer 28, which makes the contents available on data I/O pins 15 of memory system 1. Status register 26 permits the external processor to monitor certain aspects of the status of state machine 20 during memory array write and erase operations. The external processor periodically polls data I/O pins 15 to read the contents of status register 26 in order to determine whether an erase sequence (or other operation) has been completed and whether the operation was successful.
Memory system 1 verifies the status of the memory cells after performing programing or erasing operations on the cells. Verification occurs by accessing each memory element and evaluating the margins (the voltage differential between the threshold voltage of the memory cells and ground level) that the element has after the operation. The system then decides whether the element needs to be reprogrammed or erased further to achieve a desired operational margin.
The memory array needs to be programmed first in a pre-programming cycle before it can be erased. This is to avoid over-erasing the bits in some memory elements to a negative threshold voltage, thereby rendering the memory inoperative. During this cycle of pre-programming, the memory system needs to check to see if the bits are programmed to a sufficient threshold voltage level. This is accomplished by a pre-programming verification cycle that uses a different evaluation procedure than a regular read operation would use. After successful completion of the pre-programming cycle, a high voltage erase operation is executed. After the erase operation is completed, some memory systems go through an operation to tighten the distribution (reduce the variance) of memory element threshold voltages. This makes the manufacturing process easier and more reproducible. After this procedure, the memory system may perform a re-verify operation to determine if the data in the memory array has remained undisturbed.
FIG. 2 is a state diagram showing the process flow (sub-operations) of a memory system of the type shown in FIG. 1 during the pre-programming, high voltage erase, and distribution adjustment cycles of a complete erase operation. The complete erase operation starts with a pre-program cycle 200. This sub-operation programs all the elements in the memory array to a logic zero value to make sure that the erase process starts from a known cell threshold voltage level. This part of the complete erase operation is used to reduce the possibility of over erasure of some of the memory elements during the later steps of the operation.
The pre-program cycle begins with an operation which increments the address of the memory cell which is to be pre-programmed 202. This is done because the pre-programming operation is executed on a cell by cell basis. This step is followed by a high voltage level set-up stage 204 which prepares the system for application of the high voltage levels (typically about 12 volts is applied to the gate of each memory cell and 5 volts to the drain) used for programming or erasing a cell. The high voltage level used for writing to (programming) the cell is then applied in stage 206.
The appropriate voltage levels for executing the data verification sequence (reading the data programmed in the cell and comparing it to a desired value) are applied to the appropriate circuitry at stage 208. This is followed by a program verification stage 210 which verifies that the programmed cell has a sufficient threshold voltage margin. This is typically accomplished by comparing the threshold voltage of the cell to a reference cell having a desired threshold voltage (corresponding to a logic value of 0). If the verification operation was not successful, steps 204, 206, 208, and 210 are repeated. Once the verification stage for a particular memory cell is successfully completed, it is followed by a program clean up stage 212.
Program clean up stage 212 conditions all internal nodes of the memory array to default values in order to prepare the memory system for the next operation. This concludes the pre-programming cycle for a given memory cell. The address of the cell to be operated on is then incremented at stage 202 and the process repeats itself until the last cell in a memory block to be erased is pre-programmed. At this time, the incremented address will point to the first address location in the block, which is the first address for the next operation. When this occurs, all of the memory cells have been successfully pre-programmed and control is passed to the high voltage erase cycle 220.
In the high voltage erase cycle, the memory system performs a block erase operation on all of the cells contained in a block of memory. The first stage in the cycle is a high voltage level set-up stage 222 which prepares the memory block for application of the high voltage pulse(es) used for erasing the cells. This is followed by a high voltage stage 224 in which a short duration, high voltage pulse is applied to erase all of the memory cells in the block of cells. This is followed by a set-up verify stage 226 which applies the appropriate voltage levels for the data verification stage to the corresponding circuits. The next stage is an erase verify stage 228 which verifies that the erase operation was successfully carried out on each cell in the block. This is accomplished by accessing the cells, address by address, and comparing the threshold voltage of the cell to a reference cell having a desired threshold voltage level (corresponding to a logic value of 1).
If the erase operation was not successfully carried out (a cell was not erased to the threshold voltage margin corresponding to the desired logic value), control is passed back to the high voltage level set-up stage 222 and the high voltage cycle is carried out again to erase the entire block of cells. If the erase operation was successful for the cell under consideration, the address of the memory cell is incremented 230 and the next cell is tested for verification of the erase operation. Thus, if the maximum address of the cells in the block of memory has not been reached, erase verify stage 228 is carried out on the next memory cell in the block. If the maximum address for cells in the block has been reached (meaning that all the cells in the memory block have been successfully erased), control is passed to the distribution adjustment cycle 240.
The distribution adjustment sub-operation is used to tighten the distribution (reduce the variance) of the threshold voltages of the erased memory elements. This is done by applying high voltages (i.e. 12 volts) to the gates of all the memory cells in the memory block, with the memory cell drains floating and the sources at ground potential.
The distribution adjustment cycle begins with a high voltage set-up stage 242, which is followed by a high voltage stage 244 in which the voltages used to perform the adjustment sub-operation are applied. This is followed by set-up verification 246 stage which applies the appropriate voltage levels to the corresponding circuits, and erase verification 248 stage which acts to insure that all of the erased cells are still in an erased state. If the erase verification procedure fails, a final erase 249 stage may be executed. In the final erase stage, a short erase pulse is applied to the cells in the block. After completion of the previous steps, the memory elements are checked to determine if they still contain the appropriate data. At this point the erase operation is completed.
A programming operation is carried out by following a set of steps similar to those followed in pre-program cycle 200 of FIG. 2. In particular, stages 204 through 212 of FIG. 2 describe the primary functions carried out in a regular programming operation. As a program operation is typically carried out on a specific memory cell, the increment address state 202 used in the pre-program cycle to facilitate pre-programming of every cell in the memory array is not accessed. Another difference between the programing and pre-programming operations is that in a programming operation, program verify state 210 is designed to read the programmed data and compare it to data obtained from input data latch 30, rather than to a logic value of zero, as in the pre-programming operation.
As noted, in both the pre-programming and high voltage erase cycles of a complete erase operation, and in a programming operation, the state of a memory cell is verified to determine if the operation was successfully executed. This is accomplished by an internal data verification stage which is performed under the control of the internal state machine. If a memory cell does not pass the verification stage, the pre-programming, programming, or high voltage erase stage is repeated until the cell successfully passes the verification procedure, or until the high voltage pulse counter reaches its maximum value. At this point the operation is terminated and a status bit (contained in status register 26) is set indicating a problem with the block of memory cells.
There are some situations in which a test engineer is interested in knowing the status of a memory cell which has previously been programmed or erased. For instance, memory systems of the type shown in FIG. 1 are often manufactured well in advance of their sale and/or usage in other devices. In order to check whether the memory cells have maintained their previously set threshold voltage after an extended period of time, it is useful to conduct a data verification operation on the cells. Such an operation can also be used to determine the rate at which electrons are leaking from the floating gate by performing a data verification operation with a variable reference voltage. A test engineer may also be interested in knowing the status of a memory cell or block of cells after execution of a pre-programming, programming, or erase cycle but without having the memory system repeat the cycle until it is successful. This allows an examination of the effect of the high voltage pulses used in the programming and erase operations on the threshold voltages of the memory cells.
One means of determining the status of a memory cell in such instances is to perform a read operation on the cells. The sense amplifier employed in normal reading as well as data verification operations (e.g., sense amplifier 50 of FIG. 1) is typically a differential amplifier having two input signals: a signal from the selected cell indicative of the cell""s threshold voltage, Vth, and a reference signal corresponding to a reference threshold voltage, Vref. In a normal read operation, reference voltage Vref is typically 4 volts, and the measured threshold voltage Vth is typically 3 volts or 5.5 volts, depending on whether the cell stores a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d bit. Thus, the sense amplifier operates with a substantial noise margin during a normal read operation because there is a significant voltage range between Vref and the programmed or erased threshold voltage of a cell. The use of such a noise margin allows an accurate determination of whether the memory cell is programmed or erased. However, it provides little information regarding small, but potentially important changes in the threshold voltage of the cell caused by electrons leaking from the floating gate of the cell.
One method for performing an externally controlled verification procedure is described in U.S. Patent Application Ser. No. 08/511,614, filed Aug. 4, 1995, entitled xe2x80x9cMemory Circuit for Performing Threshold Voltage Tests on Cells of a Memory Arrayxe2x80x9d, the contents of which is hereby incorporated in full by reference. In the above-identified patent application, a test mode of operation is described in which a data verification operation is performed on a memory cell by executing a read operation on the cell using a program or erase verification value for the reference voltage instead of the normal read operation value. Although this has the benefit of setting the reference voltage level at values which provide a more accurate assessment of the state of the memory cell, the method does have a disadvantage. This disadvantage will be explained with reference to FIG. 3, which is a block diagram of a prior art data input/output circuit 300 for programming memory cells of a non-volatile memory array, and for reading data indicative of the state of those cells.
As shown in FIG. 3, an input/output pad 302 is connected to circuit elements which form a data read path 304 and a data write path 306 to a memory array (not shown). Pad 302 is part of the metallization of the integrated circuit containing the memory array and is connected by means of a wire bond to a data pin of the integrated circuit package. There is one data input/output circuit 300 associated with each data input/output line of the memory, with there typically being eight or sixteen data input/output lines depending upon the memory architecture.
Read path 304 and write path 306 are electrically connected to data line 308, which connects those paths to the memory array by means of decoding multiplexer 310. Decoding multiplexer 310 functions to connect read path 304 and write path 306 to a selected one of the plurality of bit lines of the array, where one of the bit lines is represented by line 312. The selected bit line, which is determined by an address provided to the memory, is connected to the drain of the memory cell being read or programmed.
Write path 306 includes a data latch 314 for storing data input by means of pad 302. Latch 314 is activated or enabled by latch enable signal 315. The latched data is sent to data input buffer or driver 316, which produces the voltage on line 318 which is applied to the bit line of the cell to be programmed. Input buffer 316 is typically implemented in the form of a tri-statable driver having an output which can be placed in a high impedance mode and effectively disabled during a read operation. The disabling of input buffer 316 is achieved by means of tri-state control line 317.
As noted, decoding multiplexer 310 is used to access a desired memory cell in the array for purpose of reading data from or writing data to that cell. When reading a memory cell of the array, multiplexer 310 is used to access the bit line connected to the selected memory cell in the array. In the event the cell being read is in an erased state, the cell will conduct a current which is converted to a voltage on line 308. Sense amplifier 320 determines the state of the cell, i.e., whether it is programmed or erased (corresponding to a binary value of 0 or 1, respectively). This determination is based on comparing the voltage on lines 308 and 312 to a reference voltage. The outcome of this comparison between the two input voltages is an output which is either high or low, corresponding to a digital value of one or zero. The output of sense amplifier 320 is sent to output buffer 322 which drives the data to output pad 302 where it is accessed by a user.
During a normal read operation in which the reference voltage is approximately 4 volts (so that a wide noise margin is present), the large differential between the inputs to the sense amplifier results in a stable, unambiguous output. This is because noise in the circuit is generally insufficient in magnitude to produce a false positive in the output of the sense amplifier. As a result, the output is stable and the output buffer only generates an output in response to a single change in the sense amplifier signal.
However, when conducting a read operation using the reference voltage levels typically used for a data verification operation, the inputs to the sense amplifier have a much smaller differential. During an internal data verification stage of the type shown in FIG. 2 (i.e., stage 210 or 228), the reference voltage (Vref) for a programming operation verification is typically set at 5.5 volts, and an adequately programmed cell has a measured threshold voltage (Vth) greater than 5.5 volts. Since the two inputs of the sense amplifier are much closer to each other in this case than for a regular read operation, the sense amplifier""s output is more susceptible to error due to noise and the sense amplifier responds much more slowly. Similarly, during data verification following a high voltage erase operation, the reference voltage (Vref) is typically set at 3 volts and an adequately erased cell has a measured threshold voltage (Vth) less than 3 volts. In this case, the two inputs of the sense amplifier are also much closer than in a regular read operation and the sense amplifier""s output is again more susceptible to noise. With noise of sufficient magnitude to produce a false positive, noise fluctuations will cause the sense amplifier output to be unstable. The output buffer will generate an output in response to the fluctuating sense amplifier output. This produces noise on a power supply pin (corresponding to Vcc, the power supply voltage, or ground) which is fed back to the sense amplifier.
The noise fed back to the sense amplifier can alter the output of the sense amplifier due to the small noise margin of the data input/output circuit when used with data verification reference voltage levels. Thus, while this test mode of data verification is superior to a normal read operation, it is still susceptible to error owing to the noise produced by the output buffer. Another disadvantage of this externally controlled data verification procedure is that it requires the test engineer to specify the address(es) of the memory cells to be verified. This increases the time required to verify the contents of a large number of memory cells.
Yet another disadvantage of an externally controlled verification procedure which uses the regular read operation sensing path is that it requires the test engineer to specify the delay between the time the read operation is initiated and when the data indicating the state of the cell is read out. This user specified delay is unlikely to match the delay the internal state machine uses during its internally controlled verification process. The difference between the two time delays can lead to inconsistent results between the two procedures, and hence cause difficulties in correlating the results of the two verification processes.
What is desired is an apparatus which can more accurately verify the status of a programmed or erased memory cell than can be obtained by using a standard read operation. It is also desired that the apparatus not be susceptible to errors caused by noise introduced by the circuit elements used to perform the verification operation.
The present invention is directed to a memory system which includes means for verifying the contents of a memory cell contained in a memory array to determine if a shift in the threshold voltage level has occurred. In one embodiment, the memory system is placed into a test mode of operation in which an internal program or erase verify operation is executed under the control of the system""s internal state machine. Once in the test mode, the memory system steps through each memory cell, address by address, and reads the contents of the cell using the appropriate reference voltage for a programming or erase operation. A status register bit is set indicating successful completion of the verification operation for a block of memory cells. A register bit is also set if a cell fails the verification operation. The verification operation described provides a more accurate determination of the state of a memory cell than can be achieved by performing an external read operation using read operation or data verification reference voltage levels.
Further objects and advantages of the present invention will become apparent from the following detailed description and accompanying drawings.